The present invention relates, in general, to the field of integrated circuit ("IC") memory devices. More particularly, the present invention relates to a highly integrated enhanced signal processing random access memory IC device which utilizes a dynamic random access memory ("DRAM") primary memory in conjunction with a static random access memory ("SRAM") cache and on-chip refresh control function which may be conveniently supplied in an industry standard SRAM IC pin-out.
Digital signal processing ("DSP") is a term applied variously to analog signal processing performed digitally or real-time signal processing as opposed to processing performed off-line. In either case, DSP is a highly computationally intensive form of signal processing in which many arithmetic operations must be performed very rapidly. As a consequence, the choice and configuration of DSP memory components for such high throughput processing gives rise to numerous unique considerations. Among these are that the individual memory devices, or "chips" which must be addressed by the DSP components must match the overall system speed or constitute a data processing "bottleneck".
This requirement has, in part, driven the demand for and development of high speed SRAM devices. However, because the memory cell configuration of an SRAM device requires a layout of either four or six transistors per cell, as opposed to the single transistor/single capacitor cell of most DRAMs, they are inherently more costly in terms of on-chip die area requirements and cannot provide the relatively greater integration densities of conventional DRAM devices. In an attempt to provide a trade-off between cost and speed, DSP system designers will often use a combination of SRAM and DRAM devices wherein the former is primarily utilized for program memory wherein device access time is among the throughput constraints and the latter may be used for data memory in those applications wherein data can be pipelined.